Wed 10 Jan 2018 16:15 - 16:40 at Bunker Hill - Memory and Concurrency Chair(s): Azadeh Farzan

The integration of transactions into hardware relaxed memory architectures is a topic of research both in industry and academia. In this paper, we provide a general architectural framework (that includes the SC, TSO and ARM8 models) for the introduction of transactions into models of relaxed memory in hardware. Our model incorporates flexible and expressive forms of transaction abort and execution that have hitherto been in the realm of Software Transactional Memory. In contrast to Software transactional memory, we account for the characteristics of relaxed memory as a (restricted form of a) distributed system without a notion of global time. We prove abstraction theorems to demonstrate that the programmer API matches the intuitions and expectations about transactions.

Wed 10 Jan
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15:50 - 17:30: Research Papers - Memory and Concurrency at Bunker Hill
Chair(s): Azadeh FarzanUniversity of Toronto
POPL-2018-papers15:50 - 16:15
Michalis KokologiannakisNational Technical University of Athens, Greece, Ori LahavTel Aviv University, Israel, Konstantinos (Kostis) Sagonas, Viktor VafeiadisMPI-SWS, Germany
POPL-2018-papers16:15 - 16:40
Brijesh DongolBrunel University London, Radha JagadeesanDePaul University, James RielyDePaul University
Link to publication DOI Pre-print Media Attached
POPL-2018-papers16:40 - 17:05
Christopher PulteUniversity of Cambridge, Shaked FlurUniversity of Cambridge, Will DeaconARM Ltd., Jon FrenchUniversity of Cambridge, Susmit SarkarUniversity of St. Andrews, Peter SewellUniversity of Cambridge
POPL-2018-papers17:05 - 17:30
Hongjin LiangUniversity of Science and Technology of China, Xinyu FengUniversity of Science and Technology of China