The integration of transactions into hardware relaxed memory architectures is a topic of research both in industry and academia. In this paper, we provide a general architectural framework (that includes the SC, TSO and ARM8 models) for the introduction of transactions into models of relaxed memory in hardware. Our model incorporates flexible and expressive forms of transaction abort and execution that have hitherto been in the realm of Software Transactional Memory. In contrast to Software transactional memory, we account for the characteristics of relaxed memory as a (restricted form of a) distributed system without a notion of global time. We prove abstraction theorems to demonstrate that the programmer API matches the intuitions and expectations about transactions.
Conference DayWed 10 JanDisplayed time zone: Tijuana, Baja California change
15:50 - 17:30
|Effective Stateless Model Checking for C/C++ Concurrency|
|Transactions in Relaxed Memory Architectures|
Brijesh DongolBrunel University London, Radha JagadeesanDePaul University, James RielyDePaul UniversityLink to publication DOI Pre-print Media Attached
|Simplifying ARM Concurrency: Multicopy-Atomic Axiomatic and Operational Models for ARMv8|
|Progress of Concurrent Objects with Partial Methods|